EV4101【PDF 9/68 页】32-bit Microprocessor that Executes MIPS

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TinyRISC

EV4101 Microprocessor Reference Device Technical Summary

For information on DBX interfaces to other elements, such as the

TR4101, BBCC, and system logic, refer to the TinyRISC TR4101

Building Blocks Technical Manual, document number DB14-000060-00.

4.1.1 Registers

Programmers access the DBX registers by using the MTD and MFD

instructions. See Section 4.1.2, “Instructions.” All bits are read/write,

except for the Reserved bits, which are hard wired to zero. Software

should, however, always write zeros to the Reserved bits.

The registers in this section have a register number for each Debug

dr)

which are indicated in parentheses in the subsection

headings.

DCS Register (7) –

The Debug Control and Status (DCS) Register

contains the status and enable bits for the debug facilities. All status bits

(bits 4 through 0) are sticky, and debug events only set the bits if the

enable signals are set. The bits must be cleared by using an MTD

Instruction to update the DCS Register. The settings of the UD and KD

bits are always the same—setting either bit sets both bits. Reset clears

the DE and IBD bits. All other bits are unknown.

MTD Instructions have higher priority than status updates. The DBX

updates the DCS Register with MTD data if an MTD Instruction occurs

simultaneously with a status update caused by a break event.

Table 1 shows the format of the DCS Register.

Trap Enable

Setting TR causes debug events to trap to the exception

vector provided that internal breaking is enabled; that is,

IBD is cleared. When TR is cleared, no trapping occurs,

but debug status bits are still updated with debug event

information.

Table 1

DCS Register

TR UD KD Res DW DR DAE PCE DE IBD

Reserved

W R DA PC DB

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